An Investigation of bus systems in the PC
Stephen Mulcahy, 9224076 Grad Dip Comp Eng

EE6511 Computer Systems: Processors

Table of Contents


I finished a BSc in Industrial Biochemistry last year and wanted to extend my knowledge of computer software and hardware due to my career interests in Bioinformatics. Bioinformatics deals with storing and analysing the data generated by the various gene sequencing projects being carried out across the world. The ultimate goals of these gene sequencing projects is to make available the genetic blueprints of various living organisms ranging from bacteria and yeast to the genome of the human being. I find the module relevant in terms of the fact that the amount of work possible in bioinformatics is directly proportional to the processing power at hand and while much of the work done is conducted on high performance platforms such as DEC Alphas and SGIs, modern PCs are approaching the point of being applicable to the area of bioinformatics in the areas of analysis and modelling of data.

Prior to this year, my knowledge of microprocessors has been limited to any experience I have gained from hands-on work with my own PC, a 486DX2-66 with 3 ISA slots and an optional 2 shared VL-bus slots. It includes integrated video and an EIDE hard-drive controller.

Introduction - An overview of the bus

A bus is basically a collection of wires which is responsible for interconnecting the various components of a microcomputer together in order to allow the exchange of data between these components and to provide power to them. Early microcomputer systems possessed relatively simple bus systems which were often adapted on the basis of their price and availability rather than for any distinguishing technical features. Current state-of-the-art PC bus systems are the product of a number of generations of bus technology and represent the end-product of numerous manufacturers attempts to 'get it right' and establish a particular standard as common to the industry and PC platform.

Backplane bus systems typically consist of a series of circuit boards mounted perpendicularly onto a motherboard via a series of slot connectors. This design allows for the exchange of bus devices and provides great flexibility in the range of devices a system can support (provided these devices adhere to the specific standard). Devices operating on a bus can be divided into two categories, bus masters and bus slaves. Bus masters are devices capable of initiating any bus cycle (memory read/write, port addressing, etc.) and bus slaves are devices which are not capable of initiating a bus cycle but merely responding to it. A third possible category are intelligent slaves which have their own intelligent controlling devices but do not assert control over the bus. A minimal bus has to feature three types of lines,

The control lines are responsible for passing control signals across the bus which instruct the devices when to read / write data. The address lines provide the memory or I/O device addresses detailing what exact locations data is to be read from / written to and the data lines provide a channel along which the actual data is transferred.

Another important aspect of buses is their dependence on related hardware. Some buses, for instance, are processor independent and can thus accommodate any of a range of microprocessors while other bus systems are designed around specific microprocessors or families or related microprocessors.

To illustrate typical bus operation, a generic PC-type bus consisting of a minimal series of lines (address, data and control/strobe lines) will be used. This illustration uses Programmed I/O to illustrate a typical bus operation since PIO tends to be quite straightforward. The control lines are used to synchronise data transfer by providing a series of pulses. Two possible schemes of control involve providing separate READ and WRITE control lines or a STROBE synchronising line and a READ/WRITE line with one state e.g. high denoting a read and the other denoting a write e.g. low. The PC bus tends to use separate READ and WRITE control lines (in fact 2 such lines for memory access and 2 additional lines for I/O access) so that scheme is adopted for the example - The CPU is sending data to a peripheral attached to the bus. The CPU asserts a strobe on the I/O write line. This pulse indicates that the preceding address on the address line is good and the addressed peripheral begins reading data from the data bus. The data write proceeds until such time as the strobe changes it level, this signals the end of the I/O write and data ceases to be read by the peripheral after a short period of time. There are other control signals involved on real bus systems but example above illustrates the minimum signals used on a system bus.

The S-100

A small company called MITS unveiled an 8-bit microcomputer kit called the Altair in 1975. Aimed at the computer hobbyist, the Altair was built around Intel's 8080 microprocessor and included a backplane expansion bus with 100 pin edge connector sockets. The particular socket design was apparently chosen because of the availability of surplus stock from a supplier, indicating that the first personal computer bus was chosen not for its technical excellence but because it was economical and available in reasonable numbers. In the case of the S-100 bus, many of the bus lines are signals which are actually generated by the 8080 processor rather than being abstracted a level beyond the microprocessor. Typical features of the S-100 board are listed in the following,

Dimensions134mm x 254 mm
Connector 100 pin edge type

(50 on each side of the board, 3.17mm apart)

Voltage SupplyUnregulated +8V,+16V

In its time, the original S-100 bus was very popular with a large range of peripheral boards being available for it including memory boards, serial and parallel interface boards, floppy disk controller boards, video boards, music synthesiser boards and speech recognition boards.

As noted in the above table , the voltage supply on the S-100 bus was unregulated, this had both advantages and disadvantages. It made for a simpler power distribution system on the bus and a reduction in electrical interference between modules. On the other hand, this power distribution strategy required that every board have its own regulator which increases the cost of individual boards. A single, good regulator on the bus would have eliminated at least some board reliability problems. The actual location of the power pins (1, 2, 51, 52) was also questionable with any misalignment of cards leading to the possibility of serious electrical damage to the board components. This could have been prevented either by locating the pins such that no power flows if the board is misaligned or by locating the power lines between grounding lines.

The position of the clock lines in the original S-100 was also potentially problematic with the PHASE 2 CLOCK (2), PHASE 1 CLOCK (1) and 2 MHz clock signals being located near to 9 other control signals. The clock signals tend to occur continuously and have sharp rise and fall times. Unless they are shielded, they can become coupled to the adjacent lines.

The S-100 provided 16 data lines, 16 address lines (providing an maximum addressable space of 64k), 3 power-supply, 8 interrupt and 39 control lines. It actually provided many more control lines than were necessary. The 16 lines of the data bus provided 2 groups of unidirectional 8 bit lines (with one set providing data input and the other providing data output). This configuration was used as opposed to a bi-directional 8-bit group of lines, neither has any great advantage over the other particularly when a lot of S-100 devices actually recombined the signals on the boards.

Not all of the S-100 lines were clearly defined and since the S-100 could be used with a variety of processors including the Intel 8080, Zilog Z-80 and Motorola 6500 and 6800 microprocessors some lines were only generated by certain microprocessors. Also, the level of standardisation in the peripheral manufacturing industry was such that there was no specific agreement on what pins were for what. Most of the few hundred boards probably worked with most implementations of the S-100 but there was definitely some instances of conflict due to this lack of standardisation. In a nutshell, the S-100 bus became popular as manufacturers began to produce compatible boards in recognition of the popularity of the Altair. This, in turn, encouraged the makers of other microcomputers to incorporate the S-100 bus into their systems. A company called Cromemco actually coined the title S-100 (derived from 'Standard 100 bus') to give a common name to what

many manufacturers were claiming to be their own bus design.

S-100 / IEEE 696

A working party set up by the IEEE in 1983 forced a redesign and enhancement of the S-100 bus design. This was actually the first time the S-100 bus was formally specified. As well as ironing out ambiguities, the standard proposed a number of enhancements,

Other improvements to the original bus included the precise specification of all 100 lines, except 3 lines designated NDEFs (21, 65, 66) and 4 lines designated RFUs (27, 28, 69, 71) - reserved for future use. The RFUs may not be used by board makers but the NDEFs may be used as a manufacturer wishes provided that their logical function is clearly specified. The data rate of any signal on the bus was tied down to 6 MHz although in actual fact, boards capable of running at speeds of up to 10Mhz were common.

The S-100/696 bus can support 1 permanent bus master and up to 16 temporary bus masters, 4 DMA lines were designated for providing access to the temporary bus masters. Priority is dependent on the particular DMA line being accessed. In a step toward processor independence, some 8080-derived signals were deleted from the new standard such as, the interrupt enable signal (PINTE) which signalled the state of the interrupt enable flip-flop; the Wait command/control signal which when high acknowledges that the processor is in wait state (PWAIT); the Stack-status (SSTACK) output signal which, when high indicates that the address bus holds the pushdown stack address.

Even this rudimentary set of rules made a relatively large impact on the status of the S-100. It was future-proofed in a number of ways,

The S-100 was thus given a new lease of life with this standard and although there were technically superior buses in existence at the time, the S-100 found application in areas as diverse as small industrial control applications to multi-user electronic office systems running proprietary database and word-processing software. The two main reasons for its popularity were its price and the large number of manufacturers that supported it. Also, as manufacturers produce more and more boards to a certain bus specification, they tend to get better at using that bus and gain experience of its quirks, thus any manufacturer is understandably slow to migrate to other technology unless there is significant market demand coupled with sound technical reason for doing so.


IBM introduced a new bus system in their XT personal computer in 1981. The bus was of relatively simple design sporting 53 signal lines and 8 power/ground lines. It was a synchronous 8-bit bus with parity protection and edge-triggered interrupts. That is, the interrupt is signalled by the peripheral device changing the voltage state on the IRQ line (from 0 to 1 or 1 to 0). Edge-triggered interrupts can only be used by a single peripheral device i.e. a number of installed peripherals cannot share the same IRQ.

The 62 pin XT bus did not support external bus masters with the only devices that could assert control over the bus being the CPU or the DMA controller on the motherboard. The key features of the XT bus are summarised below,

The original XT bus was characterised by the simplicity of its design. It didn't provide any particularly innovative features and in a lot of respects it was limited by this simplicity (e.g. very limited number of Interrupt and DMA channels; limited maximum addressable space; narrow 8-bit data path and lack of bus master support), however it was well suited to the XT and performed quite well with the 8-bit 8088 processor around which the XT was built.

An enhanced version of the XT bus was designed for use in the IBM-AT ('Advanced Technology') which was introduced in 1984. Importantly, while this bus provided significant enhancements to the original XT bus architecture, it retained backward compatibility with the original XT bus allowing old cards to be used in ATs using the new bus which was retrospectively described as ISA (Industry Standard Architecture). The major improvements to the XT bus that led to ISA are described below, most of these were implemented using an optional, additional connector (thus facilitating backwards compatibility).

The bus mastering was not a complete or perfect implementation due to certain limitations such as a request by a Bus master for 'Bus hand-off' requiring several cycles for completion and the master having to relinquish the bus periodically to allow memory refresh (or do the refresh itself). It is important to note that IBM made an effort to ensure backwards compatibility with the XT-bus. As mentioned, most of the new features were implemented by adding on another connector to the bus which allowed extra features to be added without disrupting existing (XT) bus functions. The AT was built around the Intel 80286 which ran significantly faster than the original 8088 so a wait-state generator was added to lengthen the bus cycle. A bypass was provided via one unused line (pin 88) on the original bus (recalling that the XT bus used a 62 pin connector but only had 53 signal lines and 8 power lines). This pin became the zero wait state line (). When this line is being pulled low, some or all of the wait states generated by the AT motherboard are removed. By putting this signal on the 62-pin connector, IBM allowed manufacturers to make fast new 8-bit boards as well as fast 16-bit boards.

The new connector added 4 new address lines (A20-A23), plus copies of three lower address lines (LA17-LA19). This duplication was necessary because the address lines on the XT bus were latched (the address signals were tied to flip-flops which maintained the address lines logic level until explicitly set to a different value) and this latching process caused propagation delays that would slow down peripheral boards. By providing a duplicate set of these address lines, the AT-bus allowed 16-bit boards to find out early in the cycle if they were being addressed which allowed 16-bit cards to signal the bus that they could accept a 16-bit cycle. This key feature of the AT buses backward compatibility meant that if the 80286 attempted to perform 16-bit access to a board, it would only do so if the correct signals were asserted by the addressed peripheral, otherwise special hardware on the motherboard takes over and causes two 8-bit cycles to be performed. Unfortunately, due to there being only 7 unlatched address lines as detailed above, this signal could only instruct the board as to which 128K region of memory was being addressed, so a lot of memory boards that didn't use a full 128K block of real-mode address space could not activate the signal and thus were prevented from using 16-bit transfers, in reality this included a lot of EMS boards and memory-mapped peripherals.

It is worth noting at this stage that the timings of the PC and AT backplanes weren't formally specified by IBM at the time (clone-makers finally defined a pseudo-standard for timings when developing the EISA bus).

There is no doubt that the ISA bus was not technically exceptional by today's standards, however, it exceeded the requirements of most users in 1984 and IBM's dominance of the mass computer market with the AT led to mass adoption of the ISA bus by both peripheral board manufacturers and clone PC makers. This popularity is attested by the continued inclusion of ISA slots in most modern PCs (albeit in coexistence with faster local bus technologies). The proliferation of many reliable 16-bit ISA bus cards for a variety of tasks that do not require faster transfer speeds or wider data paths has led to its continued use in PCs for tasks such as networking (Ethernet 3Com etherlink III and Novell NE2000 ISA cards account for a large section of the LAN market). Single user machines also typically provide services such as sound-cards and hard-disk controllers through the ISA bus. Obviously, its popularity and relative simplicity made it a good choice for both board and PC manufacturers and it remains to suitable many roles.


Up to April 1st, 1987, life in the PC world had been very simple; there were eight bits in a byte and just one bus to run it down. Of course, there were two sizes of bus: The 8-bit version and the 16-bit AT version, but there was no doubt that it was the same bus. Then, just one day later, on April 2nd, 1987, it had all changed and things would never be as simple again ....

-Chris Long, PC User

IBM discontinued their PC/AT line in 1987 to make way for the PS/2 series of "clone-killers". Amongst the many features of this new generation of PC was a brand new system bus - Micro Channel Architecture (MCA). One of the most important points to note regarding the MCA bus was that it was not backwards compatible with the ISA bus (as the ISA bus had been with the XT bus). IBM had designed a new bus architecture from scratch and for various reasons (some engineering based and some competition based) the ISA bus was no longer supported by IBM. Coupled with this was the fact that IBM set a large licensing fee on the use of MCA technology (as opposed to encouraging or at least not opposing the duplication of the ISA bus in clone-makers systems) for any manufacturer who wished to incorporate the design into its clone. This licensing fee including a retroactive fee for the use of the ISA bus technology.

MCA's key features are as follows,

Although MCA was technically capable, IBM's strong-arm tactics and the price tag of MCA cards resulted in IBM only slowly developing a market for this bus system. People who bought into MCA based systems were typically companies who were 'buying IBM', rather than buying MCA. IBM also provided an extension to the standard MCA slot by way of a video extension connector which was designed to speed up the video subsystem. The connector utilises video circuitry built onto MCA motherboards and allows added on boards to coexist with it and utilise its features. This supposedly provided a basic video system which could be relied on regardless of what add-on video card was present but in theory, the video extension was as proprietary as the bus system that spawned it and it never featured prominently in the video scene. In the two years following the introduction of MCA, only a few of the large clone manufacturers released MCA based machines, Apricot and Olivetti were two of the main supporters of IBM's new bus technology (and even Olivetti turned out to be burning both ends of the candle, playing an active role in the development of a competing bus standard, EISA). In September 1988, a competing bus technology was introduced by Compaq, dubbed EISA for Extended Industry Standard Architecture.


This architecture was the clone-makers response to IBM's proprietary, licensed MCA. Compaq, back by the 'Gang of Nine' - Wyse, AST Research, Tandy, Compaq, Hewlett-Packard, Zenith, Olivetti, NEC and Epson, announced a 32-bit bus extension to ISA which retained full compatibility with ISA. As with the XT to AT bus transition, extra functionality was provided by adding extra connectors to the AT bus. EISA features include,

The new pins for the EISA bus were physically placed between the pins of the ISA bus. The EISA connector/socket was designed so that ISA cards inserted rest on a set of tabs which prevent ISA cards making any physical contact with EISA lines (which could possibly have occurred due to misalignment or mis-insertion of ISA cards otherwise). EISA cards carried a number of slots which allowed them to descend and make contact with the EISA lines.

The main signal lines added to the ISA standard to create the EISA standard are indicated below,

M-10Distinguishes between an EISA memory cycle and an EISA I/O cycle
Indicates the start of an EISA bus cycle
Provides timing control within an EISA bus cycle
Indicates that a master is capable of performing burst cycles
Indicates that a slave is capable of accepting burst cycles.
EX32, EX16Indicate that a slave is an EISA board and can support a 32-bit or 16-bit cycle respectively. If neither of these signals is asserted at the beginning of a cycle, the bus falls back to an ISA compatible mode for that cycle.
Asserted by potential master number n to request the bus
Indicates to master n that it has been granted the bus

An important feature of the EISA bus is that the host or any bus master can access any memory device or peripheral in the system, even if their bus widths differ. As indicated in the features list, for sheer speed EISA excelled providing a maximum 32-bit data transfer rate of 33 MB/s. While EISA supports level-triggered interrupt lines, it is important to note that older ISA cards cannot share interrupts even when plugged into an EISA connector, since they rely on older edge-triggering.

Bus master support in the EISA could be described as complete as opposed to that provided in the ISA bus. The memory refresh controller, the active DMA channel with the highest priority and peripherals vying for bus control compete for ownership of the bus by means of a three-way sharing scheme controlled by the EISA arbitration unit, the Integrated System Peripheral chip. The scheme ensures that no bus master is deprived access although it is possible for low-priority DMA channels to suffer. An additional watchdog on the system is provided by the Intel's Bus Master Interface Chip (BMIC) which ensures that no one master remains in control of the bus for too long. After a certain time period elapses, the master is removed from the bus and a non-maskable interrupt is generated by the CPU.

In conclusion, with EISA and 32-bit microprocessors (Intel's 80386 and 80486), the PC had grown up. It was no longer confined to personal computing and now provided the power to act as a workstation or a unix box running a few hundred terminals.


MCA and EISA were effectively pitted against each other as soon as EISA was announced (about 2 years after MCA's debut). This was to be a battle not only of the bus but of IBM's control of the PC market. If a group of clone-makers could successfully introduce a new bus standard (more appropriately, a new set of extensions to an old standard) that thrived at the expense of IBM's proprietary standard then the market could break free of IBM's dominance.

Technically, the MCA and EISA were both 32-bit buses and provided similar maximum address space but there were important differences,

Raw Bandwidth20 MB/s 33 MB/s
Mode of communicationAsynchronous Synchronous
Physical Dimensions of cards (length x width) 292.1mm x 88.2 mm333.5 mm x 127.0 mm

One of the problems MCA would have given board-makers stemmed from its physical size. EISA cards provided nearly double the surface area afforded by MCA cards eliminating the need for expensive integration to build the same function in a smaller area. Power supply is also an important factor of comparison, an EISA adapter can use more than twice the power of an MCA adapter. This makes peripherals simpler and cheaper to implement in EISA.

EISA, in particular Intel's EISA chipset only supported the 80386 and 80486 chips in its own attempt to discourage the use of clone 286 processors in advanced machines while MCA featured on some 80286 based PS/2's as well as 80386 and 80486 machines. At the end of the day however, IBM remained the main supplier of both MCA cards and MCA-based PCs while EISA boxes could be bought safely in the knowledge that older ISA cards could be installed in them until faster cards became available. In general, EISA could have been said to have won the war since in instances where speed was an issue, EISA was the 32-bit bus of choice e.g. Graphics intensive systems. It's worth noting, however, that EISA never achieved the kind of market penetration envisaged by Compaq where it would replace ISA bus systems entirely, rather ISA continued to thrive in the low end of the market. By the time standard PCs were reaching the limits of ISA bus technology for tasks such as graphics, the local bus was beginning to show up effectively allowing standard PCs to bypass EISA technology.

Local Bus

The Local bus architecture takes a slightly different approach to that used by System I/O buses such as ISA, MCA and EISA by taking cards off of the expansion bus and connecting them directly to the CPU or across a bridge (integrated circuits that serve as signal amplifiers and repeaters) to the CPU. This eliminates the bottleneck of data throughput which existed when everything sat on an 8MHz bus. While 8MHz was fast enough for some devices, the performance of peripherals such as video adapters and hard-disk controllers was suffering by the early nineties. The solution was to give speed and bandwidth critical devices better access to the CPU and memory while allowing slower and older peripherals to remain on the ISA expansion bus. This was implemented by placing the ISA bus controller itself onto the local bus thus bridging the divide between local bus and slow peripherals. This was important, as had been proved by previous efforts such as IBM with MCA which neglected backwards compatibility with subsequent consequences for its popularity. Thus, most local bus implementations officially supported the bridging of older buses via a buffering scheme of some type. The two main contenders for the local bus market were VL-bus and PCI. There also existed various non-standard local bus implementations and non-specified architectures. Its important to consider that the development of processor direct buses was motivated by two main factors,


The first standard for local buses introduced in August, 1992 was the VESA local bus (or VL-bus). VESA (Video Electronic Standards Association) represented a group of over 100 companies who came up with a specification for a local bus implementation. The key features of VL-bus are summarised below,

The VL bus was a long way from the decade old ISA bus, both in terms of its performance and its design. Not only was it fully specified but it was designed with the future in mind. The VL-bus 2.0 specification even outlined a 64-bit data bus standard. When it was introduced, VL-bus was the system of choice for premium graphics performance as was intended. Manufacturers had been slow to support any of the proprietary local buses due to fears of investing heavily in technologies that could become obsolete overnight. VL-bus provided a reliable platform on which manufacturers could base their more advanced graphics adapters.

One of the design intentions with VL-bus was to come up with a specification that allowed for the design of boards which used existing chipsets and very little glue logic chips which increase card costs. This was a bonus to manufacturers and users alike in that as well as offering high performance cards, they could offer them at a low price, lower in fact than similar EISA cards.

Clearly VL-bus was a winner, at least in the short-term for this is how many in the industry viewed it, particularly Intel who were working on their own local bus implementation, PCI. VESA proposed that VL and PCI could live in harmony with the bridging capabilities of VL allowing both buses to coexist in a system. Intel agreed that this was possible but posed the rather obvious question of why one would want both. Intel viewed the VL-bus as technology based on 11 year old PC architecture. It was essentially a quick fix in their view, a product of the compromise between different manufacturers. Another potential problem with VL-bus is that the bus is driven directly by the CPU and Intel discouraged the placing of cards directly on the CPU bus since the output signals of the 80x86 are not designed to drive the heavy loads usually associated with a bus and card structure. The VL-bus specification was designed to ensure that no damage was possible but the argument existed that a badly-designed card could damage a system.


In 1992, Intel announced its own local bus technology dubbed Peripheral Component Interface (PCI) to challenge VESA's VL-bus. Intel had designed PCI from the ground up rather than implementing it as an enhancement or quick fix to the bandwidth problems occurring in the PC. Intel claimed they had spent over 2000 hours in simulations of the PCI bus on sophisticated SPICE software which allowed them to analyse potential problems with the PCI signals and modify the basic design to smooth out these flaws. The PCI standard was turned over to the PCI Special Interest Group making it an open standard. One of PCI's features is that of not being quite as local to the CPU as VL-bus, instead it operates over a bridge to the CPU bus, this has the added advantage of making it totally processor independent with a bridge chipset abstracting the CPU signals. Nonetheless, PCI is a local bus implementation. Its key features are listed below,

The 66MHz bus speed has actually been implemented on some of Intel's newer PCI chipsets (e.g. Triton II) but as per the PCI 2.1 specification, the bus will only operate at 66MHz if all peripherals are operating at this rate, otherwise it reverts to 33MHz operation. As with VL-bus, the system I/O bus can be bridged to the PCI bus to include support for the older ISA and EISA card types. This technology has even been used to implement VL to PCI bridging schemes which provide both types of local bus on the same system.

The PCI bus defines three types of address space, the two usual ones of memory and I/O and an additional space for configuration information. Each PCI device is equipped with a 256-byte area, which includes details about the device and it's type i.e. network adapter, disk-controller, graphics adapter. At system start-up, this configuration area is scanned for each PCI device and each device is assigned a unique base address and interrupt number. PCI uses the one bus for both address and data signals by multiplexing them i.e. the same electrical conducting paths are used to carry both signals although not at the same time. An additional signal line indicates whether address or data information is on the bus. This multiplexing allows the PCI board to have a relatively small number of pin-outs, which decreases the size of the connector and also decreases the area of the motherboard used by the card.

PCI was obviously designed to be future-proof with features such as 66MHz bus speed and 64-bit bus widths being assessable when the need arises and the computer industry in general has endorsed the design by supporting it. Companies has varied as Apple and Digital have plans to or already include PCI in their machines. (Apples latest generation of Power Macintoshes use PCI instead of NuBus and DEC has gone so far as to implement built in PCI support to some of its RISC chips).

VL Vs PCI bus

In the end, there was no real competition. VL bus provided a great improvement in video performance on 486 systems and provided manufacturers with a convenient scheme for integrating their systems. PCI on the other hand was always viewed as something that had been done right. It asserted itself as local bus leader with the advent of the Pentium PC where it acted as the backbone of the motherboard while VL-bus was slowly retired even though the VL 2.0 specification allowed for next generations processors, it just wasn't up to the job. This, coupled with the fact that Intel are responsible for the Pentium chipset gave them the opportunity to capture the market.

Peripheral buses

Traditionally, a bus was the hardware standard that governed how add-in boards would connect to the CPU and described the physical connections or connectors involved while an interface was a low-level description of the electrical signals that each side of a connection expected to see and how the hardware would interpret them. Peripheral buses can be found somewhere in the gray area between the two in terms of definition. In terms of function, peripheral bus generally describes a scheme for connecting peripherals such as hard-drives, scanners, cd-roms and various other storage devices. Peripheral buses are driven by a controller which typically resides on the local bus although older ISA versions of most peripheral bus controllers also exist.


This is probably the oldest peripheral bus still in common use today. The Small Computer Systems Interface provides a scheme for connecting devices such as disk storage devices and scanners to small and medium-sized computers. The SCSI specification is controlled by the American National Standards Institute (ANSI) and allows the connection of up to 7 devices to a computer. It originally became popular in Apple Macintoshes in 1984 but it is commonly found in IBM-PCs today also. The SCSI specification has been revised twice with the introduction of SCSI-2 and SCSI-3 as well as the original SCSI specification. SCSI-3 is still not fully ratified however, and most available devices conform to SCSI, with newer devices supporting subsets of the SCSI-2 standard.

The key features of SCSI are as follows,

SCSI-2 improved on the original standard in a number of areas, giving an improvement in flexibility and higher performance. The bus-width was increased to include 16 and 32 bit buses. With a maximum speed of 10MB/s on the 8-bit bus, speeds up to 40MB/s are supported on the 32-bit bus. The SCSI-2 specification allows any of the above combinations thus giving rise to a number of different subsets of SCSI-2,

Narrow SCSI8-bit version of SCSI
Wide SCSI16 and 32 bit versions of SCSI-2
Fast SCSISCSI-2 that supports 10MB/s speed

These implementations can be combined to give various different versions such as Fast-Wide SCSI for instance. A SCSI-3 specification is currently under development by ANSI, again including support for a faster bus. It will also implement longer cables, possibly of different types (e.g. copper, optical fibre, etc.). Support for a serial version of SCSI-3 is also being worked on.


Integrated Drive Electronics or IDE was developed by Western Digital and Compaq as a disk interface. It was derived from older disk interface controllers. It is not strictly speaking, a bus architecture (although some features of EIDE make it as nearly as much bus as SCSI is), but it serves as an interesting comparison to SCSI. The two features which made it the most popular disk interface in PCs are its ease of use and its price. It's key features are listed below,

1994 saw the introduction of Enhanced IDE (EIDE) which upgraded the standard to allow IDE to be used with current technologies and to improve its speed performance. Improvements include,


SCSI is a powerful peripheral bus that allows for a large number and type of devices and quite high transfer rates. But this performance is gained at a price. Most typical PCs of today come with EIDE interfaces as standard on the motherboard while SCSI requires the addition of a SCSI controller card. This represents an additional expense which is incurred in obtaining higher performance. SCSI drives typically cost significantly more than EIDE drives of the same capacity. SCSI's main advantage lies in the number and types of devices it can support (EIDE does not support the connection of devices such as scanners). SCSI also wins out in situations where it is necessary to place devices outside the computer case i.e. when all available drive bays are full. SCSI is typically found in network servers and high-power machines where additional features such as RAID (Redundant Array of Inexpensive Disks) which provide greater data reliability are of us. Unless a user requires these features however, (and todays typical PC user doesn't) EIDE is the peripheral bus of choice for general use.


There is a large range of different PC bus systems found in todays PCs. These bus systems have evolved from "one PC one bus" architectures which were prevalent in the early PCs to systems today which are built around a number of different buses, each of which is used for particular features it offers e.g. in a typical PC on the market from a vendor such as Dell Computer Corporation today, at least ISA and PCI will be supported with either an integrated EIDE disk controller or a SCSI controller also being available. The ISA bus persists in order to accommodate older cards and cards which do not require the advanced features or speed of the PCI local bus. Typically, these buses will reside on top of the PCI local bus.

An overview of the evolution of bus technologies leads to the conclusion that we there have been a series of jumps in design. The first generation of PC's used a badly defined bus standard (S-100) that was chosen more for convenience than any distinguishing performance features. ISA was the next generation of PC bus and represented a predefined (albeit loosely) bus scheme that was designed to be used in the PC, rather than being adapted for use from another system. EISA was effectively an enhanced version of ISA rather than a new generation. MCA was a standard defined from the ground-up but never really gained popular support due to the pricing and licensing strategy adopted by IBM. Thus, from an evolutionary point of view, MCA could be seen to represent the third-generation of PC bus architectures, however, given the similarities between MCA (in terms of its physical design and the features it offered), it is preferable to view it as a distant ancestor of third generation technologies which were introduced with local bus. PCI is the definite winner in local bus stakes, providing a standard that will probably see PCs well into the next decade. PCI was a designed from the ground up bus that arrived on the market at a time when its features were needed and appreciated and didn't represent a rehash of earlier technologies.

Advances in bus design are intrinsically linked to two things,


Copyright © 1997 by Stephen Mulcahy ( )